Silicon Power So-Dimm DDR2-800 2Gb

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Silicon Power So-Dimm DDR2-800 2Gb Silicon Power So-Dimm DDR2-800 2Gb Silicon Power So-Dimm DDR2-800 2Gb
Silicon Power So-Dimm DDR2-800 2Gb Silicon Power So-Dimm DDR2-800 2Gb Silicon Power So-Dimm DDR2-800 2Gb
SILICON POWER
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The SP002GBSRU800S02 is a 128M x 8bits Double Data Rate 2 SDRAM high-density for DDR2-800. The SP002GBSRU800S02 consists of 16pcs CMOS 128Mx8 bits Double Data Rate 2 SDRAMs in 60 ball FBGA...
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itc: 111003010 / sku: SP002GBSRU800S02 / ean: 4710700393000
Price last updated on 2015/02/10
Weight & dimensions
Package type
SO-DIMM
Features
Certification
RoHS
Memory
SPD profile
Unbuffered memory
Module configuration
256M x 64
Lead plating
Gold
ECC
Memory voltage
1.8 V
CAS latency
5
Memory layout (modules x size)
1 x 2 GB
Memory form factor
200-pin SO-DIMM
Component for
Notebook
Memory clock speed
800 MHz
Internal memory type
DDR2
Internal memory
2 GB
The SP002GBSRU800S02 is a 128M x 8bits Double Data Rate 2 SDRAM high-density for DDR2-800. The SP002GBSRU800S02 consists of 16pcs CMOS 128Mx8 bits Double Data Rate 2 SDRAMs in 60 ball FBGA packages, and a 2048 bits serial EEPROM on a 200-pin printed circuit board. The SP002GBSRU800S02 is a Dual In-Line Memory Module and is intended for mounting into 200-pin connector sockets. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges of DQS. Range of operation frequencies, programmable latencies allow the
same device to be useful for a variety of high bandwidth, high performance memory system
applications.

- Fast data transfer rates: PC2-6400.
- 200-pin, unbuffered dual in-line memory module.
- VDD = VDDQ = +1.8V, VDDSPD = +1.7V to +3.6V.
- JEDEC standard 1.8V I/O (SSTL_18-compatible).
- Differential data strobe (DQS, /DQS) option.
- Four-bit prefetch architecture.
- DLL to align DQ and DQS transitions with CK.
- Multiple internal device banks for concurrent operation.
- Programmable /CAS latency (CL).
- Posted /CAS additive latency (AL).
- WRITE latency = READ latency - 1 tCK.
- Programmable burst lengths: 4 or 8.
- Adjustable data-output drive strength.
- ?64ms, 8,192-cycle refresh.
- ?On-die termination (ODT).
- ?60ball FBGA Leaded & Pb-Free (RoHS compliant) package.